1. Field of the Invention
The present invention is directed to a circuit which selectably combines power of two coefficients for interpolation and filter control and, more particularly, to a circuit capable of producing a linear interpolation commonly used in digital signal processing of color signals where the invention reduces the integrated circuit chip area used by the interpolation circuit.
2. Description of the Related Art
Linear interpolation circuits are commonly used in digital signal processing systems, and particularly in image processing systems. The simplest form of linear interpolation is 1 to 2 interpolation. For example, an original image from a CCD camera might have 500 lines of pixels, while the printer or display may require 1,000 lines. The simplest way to obtain a 1000 line image is to simply replicate each camera line twice when displaying or printing. However, a preferred technique is to set the values of every second output line equal to the values of the original lines from the camera, and to set the values of "interpolated" lines in between the original lines equal to the average of the values from the two vertically adjacent original lines from the camera. This technique, referred to as 1 to 2 linear interpolation, can be implemented in hardware very easily using an adder, a hardwired bit shift to divide by 2, and a multiplexer, as illustrated in FIG. 1. In this figure the original pixel values from two adjacent original lines (line n and line n+1) from the camera are loaded into registers 10 and 12. Each register outputs 1/2 the original value by hardwired shifting. For example, if the input signal is a ten bit signal then the most significant nine bits are passed to the adder as the least significant bits of the 10 bit adder input and the most significant bit of the adder input is set to zero. In this divide by shifting type operation, if a 1/4 value is needed, the two most significant bits of the next stage are set to zero and the eight most significant bits are supplied to the least significant bits of the next stage, if a 1/8 value is needed, the three most significant bits of the next stage are set to zero and only the seven most significant bits are supplied to the least significant bits of the next stage, and so on for other binary divisions. The adder 14 stores the result of the addition in a register 16. A multiplexer 18 then alternately stores either the original pixel values or the linearly interpolated values into an output register 20 depending on whether the output line number is even or odd. In this operation, the addition of the shifted original pixel values is performed before the multiplex operation.
A 1 to 4 linear interpolation is a common operation in many image processing applications. Two such circuits are used in a digital signal processor chip produced by Eastman Kodak Company as described in the U.S. Patent previously mentioned. The general operation of a 1 to 4 interpolation technique is illustrated in FIG. 2. For each original pixel 30 in the input image, the circuit computes four "output" pixel values. One of the output pixel values 30 equals the original pixel 30. The other three output pixel values 32, 34 and 36 are linearly weighted combinations of the values of the nearest original pixels on the left and the right, if horizontal interpolation is being performed or top and bottom if vertical interpolation is being performed. The weights are 3/4 times the left pixel plus 1/4 times the right pixel for the first produced pixel 32, 1/2 times the left pixel plus 1/2 times the right pixel for the second produced pixel 34, and 1/4 times the left plus 3/4 times the right for the third produced pixel 36.
FIG. 3A shows one of the two identical "horizontal chroma interpolator" circuits shown as FIG. 7 of the Patent mentioned above. The two "original" pixel values are loaded into the top two registers 40 and 42 every fourth master clock cycle (See FIG. 3B). A 4 to 1 multiplexer 44 which is actually composed of three 2 to 1 multiplexers, is used to set the output equal to one of four values (See FIG. 3C). When CHROMAPIX(2)=00, the value in register 42 is used. When CHROMAPIX(2)=01, the output is set equal to 3/4 of the register 42 pixel value plus 1/4 of the register 40 pixel value. When CHROMAPIX(2)=10, the output equals 1/2 of the register 42 pixel value plus 1/2 of the register 40 pixel value. When CHROMAPIX(2)=11, the output equals 3/4 of the register 40 pixel value plus 1/4 of the register 42 pixel value. The implementation shown in FIG. 3A is the simplest prior art 1 to 4 interpolation circuit known and includes seven registers 40, 42, 46, 48, 50, 52 and 54, five adders 56, 58, 60, 62 and 64, and a 4 to 1 multiplexer or three 2 to 1 multiplexers.
Another method of performing a linear interpolation is to use multipliers and interpolation coefficients stored in registers. This approach uses even more chip area than the approach discussed above.